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AS1121
Datasheet - D e t a i l e d D e s c r i p t i o n
Greyscale PWM Operation
The falling edge of the OEN signal initiates a greyscale PWM cycle. The first GSCLK pulse after the falling edge of OEN increments the grey-
scale counter by one and switches on any OUT n whose greyscale value does not equal zero. Each subsequent rising edge of GSCLK incre-
ments the greyscale counter by one.
The AS1121 compares the greyscale value of each OUT n channel with the greyscale counter value. All OUT n whose greyscale values equal the
counter values are switched off. A OEN = 1 signal after 4096 GSCLK pulses resets the greyscale counter to zero and completes a greyscale
PWM cycle (see Figure 24) .
Figure 24. Greyscale PWM Cycle Timing Diagram
all LED’s ON
all LED’s OFF
Greyscale PWM
Cycle n
Greyscale
PWM
Cycle n +1
OEN
t WH1
t WL1
t H4
t WH3
t SU4
GSCLK
1
2
3
4096
t W1
OUT0:OUT3
t PD2
t PD1
t PD2
Current
OUT4:OUT7
Current
OUT8:OUT11
Current
OUT12:OUT15
t PD2 +t d
t PD2 +2xt d
t PD2 +3xt d
t PD2
Current
XERR
Output Delay
To minimize the ripple on the inrush current, the outputs are delayed and are not switching at the same time. The 16 channels of the AS1121 are
combined in groups of 4. The channels within the groups OUT0:OUT3, OUT4:OUT7, OUT8:OUT11, OUT12:OUT15 are switching at the same
time. Between the 4 groups a delay of t d = 25ns (typ.) is implemented. On request this delay can be turned off (see Ordering Information on page
20) .
To increase the EMI performance the rising and falling edges of the OUTn signals are symmetrical (t R = t F = 25ns). The rise- and fall-times are
factory set and can be changed on request. For further information and requests, please contact us mailto:sales@austriamicrosystems.com.
www.austriamicrosystems.com/AS1121
Revision 1.01
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